A slew-rate controlled output driver using pll as compensation circuit-Reference-Cited by-同舟云学术

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A slew-rate controlled output driver using pll as compensation circuit

Published:2003-07 Issue:7 Volume:38 Page:1227-1233
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Soon-Kyun Shin ,Seok-Min Jung ,Jin-Ho Seo ,Myeong-Lyong Ko ,Jae-Whui Kim

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/27195/01208473.pdf?arnumber=1208473

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A SSN reduction technique for single-ended I/O, parallel link system;2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan);2023-07-17

2. A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique;IET Circuits, Devices & Systems;2022-10-30

3. A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-11

4. A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-09

5. 2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations;Journal of Circuits, Systems and Computers;2019-08-05

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