A 0.13-$\mu$m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN-Reference-Cited by-同舟云学术

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A 0.13-$\mu$m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

Published:2009-11 Issue:11 Volume:44 Page:3146-3162
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ha Kyung-Soo,Kim Lee-Sup,Bae Seung-Jun,Park Kwang-Il,Choi Joo Sun,Jun Young-Hyun,Kim Kinam

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5308580/05308593.pdf?arnumber=5308593

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08

2. A SSN reduction technique for single-ended I/O, parallel link system;2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan);2023-07-17

3. An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-04

4. A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-01

5. A quadrature LO-generator using an external single-ended clock receiver for dual-band WLAN applications;IEICE Electronics Express;2021-05-25

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