A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface-Reference-Cited by-同舟云学术

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A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

Published:2008-01 Issue:1 Volume:43 Page:132-140
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Villa Corrado,Vimercati Daniele,Schippers Stefan,Polizzi Salvatore,Scavuzzo Andrea,Perroni Maurizio,Gaibotti Maurizio,Sali Mauro Luigi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4443178/04443214.pdf?arnumber=4443214

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application;2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2019-04

2. A 58-nm 2-Gb MLC “B4-Flash” Memory with Flexible Multisector Architecture;IEEE Journal of Solid-State Circuits;2017-05

3. On-Wafer Analog Pulse Generator for Fast Characterization and Parametric Test of Resistive Switching Memories;IEEE Transactions on Semiconductor Manufacturing;2014-05

4. Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications;ISRN Electronics;2013-05-25

5. A Low-Voltage 1 Mb FRAM in 0.13 $\mu$m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin;IEEE Journal of Solid-State Circuits;2012-01

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