Author:
Fuji Yang ,O'Neill J.H.,Inglis D.,Othmer J.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
22 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Up-Conversion of Clock Phase Noise in Plesiochronous Data Links;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-12
2. Receiver Fundamentals;Analysis and Design of Transimpedance Amplifiers for Optical Receivers;2017-09-22
3. Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies;JSTS:Journal of Semiconductor Technology and Science;2013-08-31
4. Design and Realization of CDR and SerDes Circuit Used in BLVDS Controlling System;Recent Advances in Computer Science and Information Engineering;2012
5. A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters;JSTS:Journal of Semiconductor Technology and Science;2009-06-30