An 80 mW 40 Gb/s 7-TapT/2-Spaced Feed-Forward Equalizer in 65 nm CMOS-Reference-Cited by-同舟云学术

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An 80 mW 40 Gb/s 7-TapT/2-Spaced Feed-Forward Equalizer in 65 nm CMOS

Published:2010-03 Issue:3 Volume:45 Page:629-639
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Momtaz Afshin,Green Michael M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5419169/05419189.pdf?arnumber=5419189

Cited by 44 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fractionally-Spaced Equalizers as Clock and Data Recovery Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

2. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01

3. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024-01

4. Linear broadband interference suppression circuit based on GaN monolithic microwave integrated circuits;IET Circuits, Devices & Systems;2023-07

5. 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

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