A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking-Reference-Cited by-同舟云学术

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A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking

Published:2004-04 Issue:4 Volume:39 Page:613-621
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Miki Y.,Saito T.,Yamashita H.,Yuki F.,Baba T.,Koyama A.,Sonehara M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/28587/01278579.pdf?arnumber=1278579

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis;IEEE Journal of Solid-State Circuits;2019-10

4. Power budget enhancement in NG-EPON system employing novel twisted-PAM4;Optics Communications;2018-03

5. Decision-Point Control;Analysis and Design of Transimpedance Amplifiers for Optical Receivers;2017-09-22

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