Semiconductor Memory Technologies: State-of-the-Art and Future Trends
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/2/10488870/10488872.pdf?arnumber=10488872
Reference15 articles.
1. Semiconductor Memory Devices and Circuits
2. Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
3. 3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
4. A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement
5. A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μ A Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature
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