A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement-Reference-Cited by-同舟云学术

A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Kim Woongrae¹,Jung Chulmoon¹,Yoo Seongnyuh¹,Hong Duckhwa¹,Hwang Jeongjin¹,Yoon Jungmin¹,Jung Ohyong¹,Choi Joonwoo¹,Hyun Sanga¹,Kang Mankeun¹,Lee Sangho¹,Kim Dohong¹,Ku Sanghyun¹,Choi Donhyun¹,Joo Nogeun¹,Yoon Sangwoo¹,Noh Junseok¹,Go Byeongyong¹,Kim Cheolhoe¹,Hwang Sunil¹,Hwang Mihyun¹,Yi Seol-Min¹,Kim Hyungmin¹,Heo Sanghyuk¹,Jang Yeonsu¹,Jang Kyoungchul¹,Chu Shinho¹,Oh Yoonna¹,Kim Kwidong¹,Kim Junghyun¹,Kim Soohwan¹,Hwang Jeongtae¹,Park Sangil¹,Lee Junphyo¹,Jeong Inchul¹,Cho Joohwan¹,Kim Jonghwan¹

Affiliation:

1. SK hynix Semiconductor,lcheon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067805.pdf?arnumber=10067805

Reference5 articles.

1. A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme;bae;ISSCC,2012

2. ProTRR: Principled yet Optimal In-DRAM Target Row Refresh

3. BLACKSMITH: Scalable Rowhammering in the Frequency Domain

4. Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

5. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

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3. CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

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