A Digital Delay Model Supporting Large Adversarial Delay Variations
Author:
Affiliation:
1. TU Wien,Embedded Computing Systems Group (E191-02),Vienna,Austria
Funder
Austrian Science Fund
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10139314/10138940/10139680.pdf?arnumber=10139680
Reference15 articles.
1. A faithful binary circuit model with adversarial noise;függer,2020
2. A digital delay model supporting large adversarial delay variations;öhlinger,2023
3. A faithful binary circuit model with adversarial noise
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1. Accurate Hybrid Delay Models for Dynamic Timing Analysis;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
2. A Hybrid Delay Model for Interconnected Multi-Input Gates;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06
3. A Digital Delay Model Supporting Large Adversarial Delay Variations;2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS);2023-05-03
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