FPGA Implementation of Low-Latency Recursive Median Filter
Author:
Affiliation:
1. School of Information Engineering, Southwest University of Science and Technology,Mianyang,China
2. School of Computer Science and Technology, Southwest University of Science and Technology,Mianyang,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9973804/9974184/09974273.pdf?arnumber=9974273
Reference16 articles.
1. Fpga implementation of a 3/spl times/3 window median filter based on a new efficient bit-serial sorting algorithm;lee;7th Korea-Russia International Symposium on Science and Technology Proceedings KORUS 2003 (IEEE Cat No 03EX737) KORUS-03,2003
2. A bit-level systolic array for median filter
3. Design and implementation of a novel algorithm for general purpose median filtering on FPGAs
4. Comparison of 2D median filter hardware implementations for real-time stereo video
5. Low Hardware Complexity Pipelined Rank Filter
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