Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration-Reference-Cited by-同舟云学术

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration

Published:2022-12-05 Issue: Volume: Page:
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Container-title:2022 International Conference on Field-Programmable Technology (ICFPT)
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Author:

Park Dongjoon¹,Xiao Yuanlong¹,DeHon Andre¹

Affiliation:

1. University of Pennsylvania,Dept. of Electrical and Systems Engineering,Philadelphia,PA,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9973804/9974184/09974201.pdf?arnumber=9974201

Reference36 articles.

1. OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs

2. Case for Fast FPGA Compilation Using Partial Reconfiguration

3. Deflection-routed butterfly fat trees on FPGAs

4. HiPR: High-level partial reconfiguration for fast incremental FPGA compilation;xiao;Proceedings of the International Conference on Field-Programmable Logic and Applications 2022,0

5. A Deep-Learning Framework for Predicting Congestion During FPGA Placement

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2. REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

3. AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

4. FPGA Power Consumption Optimization Methods Analysis;2023 International Conference on Electromechanical and Energy Systems (SIELMEN);2023-10-11

5. ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation;ACM Transactions on Reconfigurable Technology and Systems;2023-09-14