Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration
Author:
Affiliation:
1. University of Pennsylvania,Dept. of Electrical and Systems Engineering,Philadelphia,PA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9973804/9974184/09974201.pdf?arnumber=9974201
Reference36 articles.
1. OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs
2. Case for Fast FPGA Compilation Using Partial Reconfiguration
3. Deflection-routed butterfly fat trees on FPGAs
4. HiPR: High-level partial reconfiguration for fast incremental FPGA compilation;xiao;Proceedings of the International Conference on Field-Programmable Logic and Applications 2022,0
5. A Deep-Learning Framework for Predicting Congestion During FPGA Placement
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