CMOS low-power analog circuit design-Reference-Cited by-同舟云学术

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CMOS low-power analog circuit design

Published: Issue: Volume: Page:
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Container-title:Emerging Technologies: Designing Low Power Digital Systems
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Author:

Enz C.C.,Vittoz E.A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/3737/10935/00508872.pdf?arnumber=508872

Cited by 42 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A design-oriented single-piece short-channel MOSFET model;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. WASA: a low power and high integration readout ASIC for TPCs in 65 nm CMOS;Journal of Instrumentation;2024-04-01

3. CMOS Adaptive Biased Second Generation Voltage Conveyor;2023 International Workshop on Biomedical Applications, Technologies and Sensors (BATS);2023-09-28

4. Transconductance-to-Current Ratio Based Threshold Voltage Extraction in MOSFETs from Linear to Saturation Modes;2023 IEEE Latin American Electron Devices Conference (LAEDC);2023-07-03

5. A Low-Power Neuromorphic CMOS Delta-Sigma Modulator Featuring Tunable Background Attenuation and Potentiostatic Asynchronous Readout for Smart Amperometric Electrochemical Sensors;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

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