WASA: a low power and high integration readout ASIC for TPCs in 65 nm CMOS

Abstract

Abstract The paper presents the development of a low-power and high-integration readout ASIC (WASA) for time projection chambers (TPCs). Each channel of the ASIC consists of the analog front-end, a waveform sampling ADC and digital signal processing circuits. To reduce power consumption, a simple CR-RC shaper and a digital trapezoid filter are adopted to achieve comparable performance to a CR-RC4 shaper with much lower power. Trigger logic and data buffer have also been integrated to reduce the data bandwidth. A 16-channel prototype chip was fabricated in a 65 nm CMOS process and was tested. The test results were consistent with the simulation. At 40 MSPS sampling rate, the power consumption of the chip was only 4.94 mW per channel, including 1.38 mW from the analog front-end, 0.83 mW from the waveform sampling ADC and 2.73 mW from digital logics. The equivalent noise charge of 569 e+14.8 e/pF has been achieved. The measured dynamic range was 120 fC and the integral nonlinearity was less than 0.74%. More design details and test results will be given in this paper.