A High-Speed FPGA Implementation of AES for Large Scale Embedded Systems and its Applications
Author:
Affiliation:
1. Concordia University,Montreal,Canada
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9810981/9811103/09811140.pdf?arnumber=9811140
Reference23 articles.
1. FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
2. Design and implementation of power and area optimized AES architecture on FPGA for IoT application
3. High-Throughput Optimizations of AES Algorithm for Satellites
4. A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application
5. A Privacy-Preserving Framework for Surveillance Systems
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3. A Pipelined AES and SM4 Hardware Implementation for Multi-tasking Virtualized Environments;Lecture Notes in Computer Science;2024
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