D-Band Flip-Chip Packaging with Wafer-Level Cu-pillar Bumps-Reference-Cited by-同舟云学术

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D-Band Flip-Chip Packaging with Wafer-Level Cu-pillar Bumps

Published:2023-10-15 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
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Author:

Cao Zhibo¹,Stocchi Matteo²,Wipf Christian¹,Lehmann Jens¹,Li Lei³,Wipf Selin Tolunay¹,Wietstruck Matthias¹,Carta Corrado⁴,Kaynak Mehmet⁵

Affiliation:

1. Mikroelektronik,IHP – Leibniz-Institut für Innovative,Frankfurt Oder,Germany

2. Keysight Technologies,Böblingen,Germany

3. Cornell University,ECE Department,Ithaca,USA

4. Technische Universität Berlin,IHP – Leibniz-Institut für Innovative Mikroelektronik,Frankfurt Oder,Germany

5. Texas Instrument,Kilby Lab,Dallas,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10314857/10314859/10314877.pdf?arnumber=10314877

Reference9 articles.

1. Characterization of a low-loss and wide-band (DC to 170 GHz) flip-chip interconnect on an organic substrate

2. Flip-Chip Approach for 500 GHz Broadband Interconnects

3. Flip-Chip-Assembled $W$-Band CMOS Chip Modules on Ceramic Integrated Passive Device With Transition Compensation for Millimeter-Wave System-in-Package Integration

4. Demonstration of +100-GHz Interconnects in eWLB Packaging Technology

5. 120-GHz and 240-GHz Broadband Bow-Tie Antennas in eWLB Package for High Resolution Radar Applications

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