Fabrication of High Aspect Ratio 35 /spl mu/m Pitch Interconnects for Next Generation 3-D Wafer-Level Packaging by Through-Wafer Copper Electroplating-Reference-Cited by-同舟云学术

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Fabrication of High Aspect Ratio 35 /spl mu/m Pitch Interconnects for Next Generation 3-D Wafer-Level Packaging by Through-Wafer Copper Electroplating

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Container-title:56th Electronic Components and Technology Conference 2006
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Author:

Dixit P.,Jianmin Miao

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10951/34490/01645675.pdf?arnumber=1645675

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 8-inch wafer-level electroplating of nanotwinned copper redistribution layer for advanced packaging;2022 23rd International Conference on Electronic Packaging Technology (ICEPT);2022-08-10

2. A critical review of copper electroless deposition on glass substrates for microsystems packaging applications;Surface Engineering;2022-06-03

3. Drilling, bonding, and forming conductive path in the hole by laser percussion drilling;Precision Engineering;2020-01

4. Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices;IEEE Transactions on Components, Packaging and Manufacturing Technology;2013-09

5. Power Noise in TSV-Based 3-D Integrated Circuits;IEEE Journal of Solid-State Circuits;2013-02

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