The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories-Reference-Cited by-同舟云学术

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The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories

Published:2006 Issue: Volume: Page:
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Container-title:2006 Fortieth Asilomar Conference on Signals, Systems and Computers
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Author:

Strukov Dmitri

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4176490/4176491/04176752.pdf?arnumber=4176752

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