Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM-Reference-Cited by-同舟云学术

Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM

Published:2024-04 Issue:4 Volume:71 Page:1651-1664
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Chao¹^ORCID,Wang Zhaohao¹^ORCID,Li Shixing¹,Zhang Zhongkui¹^ORCID,Zhang Youguang¹

Affiliation:

1. Fert Beijing Research Institute, MIIT Key Laboratory of Spintronics, School of Electronics and Information Engineering, Beihang University, Beijing, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10484988/10437994.pdf?arnumber=10437994

Reference45 articles.

1. 25 nm iPMA-type hexa-MTJ with solder reflow capability and endurance >; 107 for eFlash-type MRAM;Honjo

2. Spintronics for Energy- Efficient Computing: An Overview and Outlook

3. First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories

4. Opportunities and challenges for spintronics in the microelectronics industry

5. Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

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1. Demonstration of a NAND-Like SOT-MRAM Multi-Level Cell with Two Operational Modes;2024 IEEE 24th International Conference on Nanotechnology (NANO);2024-07-08

2. BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network;IEEE Transactions on Circuits and Systems I: Regular Papers;2024