A Calibration-Free Fractional-<i>N</i> Analog PLL With Negligible DSM Quantization Noise-Reference-Cited by-同舟云学术

A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise

Published:2023-09 Issue:9 Volume:58 Page:2513-2525
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Murphy David¹^ORCID,Yang Dihang¹^ORCID,Darabi Hooman¹^ORCID,Behzad Arya²

Affiliation:

1. Broadcom Inc., Irvine, CA, USA

2. Broadcom Inc., San Jose, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10229945/10093857.pdf?arnumber=10093857

Reference44 articles.

1. A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application

2. A 104 fsrms-jitter and ?61 dbc-fractional spur 15 GHz fractional-N subsampling PLL using a voltage-domain quantization-error cancelation technique;kim;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

3. A sub-100 MHz reference-driven 25-to-28 GHz fractional-N PLL with ?250 dB FoM;yang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

4. A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter;mercandelli;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

5. A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL

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