A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology-Reference-Cited by-同舟云学术

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology

Published:2024-01 Issue:1 Volume:59 Page:8-18
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhang Bo¹^ORCID,Vasani Anand¹,Sinha Ashutosh¹,Nilchi Alireza¹,Tong Haitao¹,Rao Lakshmi P.¹,Khanoyan Karapet¹,Hatamkhani Hamid¹,Yang Xiaochen¹,Meng Xin¹,Wong Alexander¹,Kim Jun¹,Jing Ping¹^ORCID,Sun Yehui¹,Nazemi Ali¹,Liu Dean¹^ORCID,Brewster Anthony¹,Cao Jun¹^ORCID,Momtaz Afshin¹

Affiliation:

1. Broadcom Inc., Irvine, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10375801/10260232.pdf?arnumber=10260232

Reference19 articles.

1. IEEE Standard for Ethernet Amendment 4: Physical Layer Specifications and Management Parameters for 100 Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Based on 100 Gb/s Signaling

2. A 112 Gb/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR-ADC and inverter-based RX analog front-end in 7 nm FinFET;Im

3. A 460 mW 112 Gb/s DSP-based transceiver with 38 dB loss compensation for next-generation data centers in 7 nm FinFET technology;Ali

4. A 116 Gb/s DSP-based wireline transceiver in 7 nm CMOS achieving 6 pJ/b at 45 dB loss in PAM-4/duo-PAM-4 and 52 dB in PAM-2;LaCroix

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-Stage Speculative PAM4 Decision Feedback Equalizer for Short Reach Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-01