A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET-Reference-Cited by-同舟云学术

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET

Published:2022-12 Issue:12 Volume:57 Page:3646-3655
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sung Barosaim¹^ORCID,Seok Hyun-Gi¹,Kim Jaekwon¹,Lee Jaehoon¹,Jang Taejin¹,Jang Ilhoon¹,Kim Youngmin¹,Yu Anna¹,Jang Jong-Hyun¹,Lee Jiyoung¹,Bae Jeongyeol¹,Park Euiyoung¹,Lee Sungjun¹,Lee Seokwon¹,Kim Joohan¹,Kim Beomkon¹,Lim Yong¹,Oh Seunghyun¹,Lee Jongwoo¹

Affiliation:

1. System LSI Business, Samsung Electronics, Hwaseong-si, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9962295/09921404.pdf?arnumber=9921404

Reference17 articles.

1. A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET

2. A complex band-pass filter for low-IF conversion DAB/T-DMB tuner with I/Q mismatch calibration;kim;Proc IEEE Asian Solid-State Circuits Conf,2008

3. A 2.2 GHz 7.6 mW sub-sampling PLL with ?126 dBc/Hz in-band phase noise and 0.15 psrms jitter in 0.18?m CMOS;gao;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2009

4. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

5. A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

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2. A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET;IEEE Journal of Solid-State Circuits;2022-12