Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology-Reference-Cited by-同舟云学术

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

Published:2023-04 Issue:4 Volume:58 Page:1087-1093
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Yusung¹^ORCID,Ong Clifford¹,Pillai Anandkumar Mahadevan¹,Jagadeesh Harish¹,Baek Gwanghyeon¹,Rajwani Iqbal²,Guo Zheng¹^ORCID,Karl Eric¹

Affiliation:

1. Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA

2. Accelerated Computing Systems and Graphics (AXG), Intel Corporation, Folsom, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10082904/09999728.pdf?arnumber=9999728

Reference18 articles.

1. Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6 V 32 nm LP SRAM;wang;IEDM Tech Dig,2011

2. 2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads

3. A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme

4. 15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

5. 12.1 A 7 nm 256 Mb SRAM in high-K metal-gate FinFET technology with write-assist circuitry for low-VMIN applications;chang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

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