A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications
Author:
Funder
A*STAR AME Program Nanosystems at the Edge
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9237188/09138461.pdf?arnumber=9138461
Cited by 45 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Fast Transient PMOS LDO with AP3 Buffer and Shaped-Hybrid-Bias EA Techniques Achieving 8.15ps FOM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A Tri-Loop Capacitor-Less LDO with Current Feedback Loop and Super Source Follower Achieving 8-mV Undershoot and 99-dB PSR;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Research on External Capacitor-Less Low Drop-Out Regulator for Power Integrated Circuits;2024 IEEE 7th International Electrical and Energy Conference (CIEEC);2024-05-10
4. A Fast-Transient Radiation-Tolerant LDO-cum-Latching Current Limiter;IEEE Transactions on Power Electronics;2024-04
5. An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient;IEEE Journal of Solid-State Circuits;2024-02
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