A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS-Reference-Cited by-同舟云学术

A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS

Published:2023-01 Issue:1 Volume:58 Page:45-56
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sheng Kai¹^ORCID,Niu Haowei¹,Zhang Boyang¹,Gai Weixin¹^ORCID,Ye Bingyi¹^ORCID,Zhou Hang¹,Chen Congcong¹

Affiliation:

1. School of Integrated Circuits, Peking University, Beijing, China

Funder

National Key Research and Development Program of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9999561/09919826.pdf?arnumber=9919826

Reference25 articles.

1. All-Analog Adaptive Equalizer for Coherent Data Center Interconnects

2. Design of Low-Power DSP-Free Coherent Receivers for Data Center Links

3. Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver

4. Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

5. 29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS;cao;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

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