An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires-Reference-Cited by-同舟云学术

An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires

Published:2022-03 Issue:3 Volume:57 Page:932-941
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Tae-Jin^ORCID,Park Jae-Woo,Lim Hyun-Wook^ORCID,Lee Jae-Youl,Chun Jung-Hoon^ORCID

Funder

National Research and Development Program through the National Research Foundation of Korea

Ministry of Science and ICT

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9718232/09684018.pdf?arnumber=9684018

Reference20 articles.

1. A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

2. A pin-efficient 20.83 Gb/s/wire 0.94 pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12 mm for MCM packages in 28 nm CMOS;shokrollahi;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2016

3. A 1 V 7.8 mW 15.6 Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4;choi;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

4. The MIPI C-PHY Standard: A Generalized Multiconductor Signaling Scheme

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1. A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-04

2. 4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06