A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE
Author:
Affiliation:
1. Sungkyunkwan University,Department of Electrical and Computer Engineering,Suwon,Korea
Funder
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980792.pdf?arnumber=9980792
Reference6 articles.
1. A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization
2. A 1V 7.8mW 15.6Gb/s C-PHY transceiver using trilevel signaling for post-LPDDR4;choi;ISSCC,2017
3. An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 2.56-Gsymbol/s/lane MIPI C-PHY Transmission Bridge Chip for FPGA-based Pattern Generator;The Journal of Korean Institute of Information Technology;2024-07-31
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