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A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization

  • Published:2020-11 Issue:11 Volume:67 Page:2672-2676
  • ISSN:1549-7747
  • Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Lee Pil-HoORCID,Jang Young-ChanORCID

Funder

Priority Research Centers Program through the NRF

Ministry of Education

HRD Program for Intelligent Semiconductor Industry through the MOTIE

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2.56-Gsymbol/s/lane MIPI C-PHY Transmission Bridge Chip for FPGA-based Pattern Generator;The Journal of Korean Institute of Information Technology;2024-07-31

2. A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-04

3. 4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

4. A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06

5. Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-08
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