A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS
Author:
Affiliation:
1. Intel Corporation, Hillsboro, OR, USA
Funder
Intel Labs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9761850/09718586.pdf?arnumber=9718586
Reference47 articles.
1. Bandwidth enhancement for transimpedance amplifiers
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5. A Low-Noise Design Technique for High-Speed CMOS Optical Receivers
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