A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA
Funder
Semiconductor Research Corporation (SRC) Texas Analog Center of Excellence
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/4/10051119/9989508-aam.pdf
Reference30 articles.
1. A jitter-robust 40 Gb/s ADC-based multicarrier receiver front end in 22 nm FinFET;zhu;Proc IEEE Custom Integr Circuits Conf (CICC),2022
2. A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
3. Performance analysis of general charge sampling;xu;Proc IEEE Int Symp Circuits Syst (ISCAS),2003
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