Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency

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Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector

Published:2022-02 Issue:2 Volume:57 Page:573-585
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Park Kwanseo^ORCID,Shim Minkyo,Ko Han-Gon^ORCID,Nikolic Borivoje^ORCID,Jeong Deog-Kyoon^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9694622/09569750.pdf?arnumber=9569750

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A Proof-of-Concept FPGA-Based Clock Signal Phase Alignment System;Electronics;2024-08-20

3. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

4. A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11

5. A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement;IEEE Journal of Solid-State Circuits;2023-10

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