A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body Voltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output Voltage Ripple-Reference-Cited by-同舟云学术

A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body Voltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output Voltage Ripple

Published:2023-02 Issue:2 Volume:58 Page:486-496
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chen Bo-Hao¹^ORCID,Wu Tzu-Ying¹,Zheng Kuo-Lin²,Chen Ke-Horng¹^ORCID,Lin Ying-Hsi³,Lin Shian-Ru³,Tsai Tsung-Yen³

Affiliation:

1. Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2. Chip-GaN Power Semiconductor Corporation, Hsinchu, Taiwan

3. Realtek Semiconductor Corporation, Hsinchu, Taiwan

Funder

Ministry of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10027566/09816084.pdf?arnumber=9816084

Reference22 articles.

1. A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V;salem;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

2. 25.2 A 480 mA output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector with 99.99% current efficiency, 1.3ns response time, and 9.8A/mm2 current density;oh;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

3. 14.6 A 745pA hybrid asynchronous binary-searching and synchronous linear-searching digital LDO with $3.8 \times 10^{5}$ dynamic load range, 99.99% current efficiency, and 2 mV output voltage ripple;li;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

4. 20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

5. Single-inductor dual-output DC–DC converters with high light-load efficiency and minimized cross-regulation for portable devices;huang;Proc IEEE Symp VLSI Circuits,2008

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1. A Constant-Quiescent-Current and Fast-Transient CL-LDO with 99.99% Efficiency Using Dynamic Embedded Slew-Rate Enhancement Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. An Analog-assisted Fast-transient Digital LDO with a Charge-pump-based Fine Loop Achieving 0.14-mV Output Voltage Ripples;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A Fast-Transient mitigation technique for a dual-loop, linear search, self-timed, Asynchronous Digital LDO;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

5. A Capacitor-less Digital Low-Dropout Regulator with Self-Clocked Operation;IEEE Transactions on Circuits and Systems II: Express Briefs;2023