A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer
Author:
Affiliation:
1. National University of Sciences & Technology (NUST),Islamabad,Pakistan
2. New York University Abu Dhabi,Abu Dhabi,UAE
3. The Catholic University of Korea,Bucheon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558004.pdf?arnumber=10558004
Reference16 articles.
1. A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
2. Architectural Advancement of Digital Low-Dropout Regulators
3. A Fast-Transient Fully-Integrated Digital LDO With Current-Estimation Algorithm Based Coarse Loop
4. Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On–Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm
5. A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications
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