A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme-Reference-Cited by-同舟云学术

A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme

Published:2024-01 Issue:1 Volume:59 Page:116-127
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hsu Hung-Hsi¹^ORCID,Wen Tai-Hao¹,Huang Wei-Hsing¹,Khwa Win-San²,Lo Yun-Chen¹^ORCID,Jhang Chuan-Jia¹,Chin Yu-Hsiang¹,Chen Yu-Chiao¹,Lo Chung-Chuan¹,Liu Ren-Shuo¹^ORCID,Tang Kea-Tiong¹^ORCID,Hsieh Chih-Cheng¹^ORCID,Chih Yu-Der²,Chang Tsung-Yung Jonathan²,Chang Meng-Fan²^ORCID

Affiliation:

1. Department of Electronic Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan

2. Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan

Funder

Taiwan Semiconductor Manufacturing Company (TSMC)-Joint Developed Project

National Science and Technology Council (NSTC) of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10375801/10268404.pdf?arnumber=10268404

Reference29 articles.

1. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

2. A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

3. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

4. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

5. A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications