15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips-Reference-Cited by-同舟云学术

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Published:2020-02 Issue: Volume: Page:
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Container-title:2020 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Su Jian-Wei,Si Xin,Chou Yen-Chi,Chang Ting-Wei,Huang Wei-Hsing,Tu Yung-Ning,Liu Ruhui,Lu Pei-Jung,Liu Ta-Wei,Wang Jing-Hong,Zhang Zhixiao,Jiang Hongwu,Huang Shanshi,Lo Chung-Chuan,Liu Ren-Shuo,Hsieh Chih-Cheng,Tang Kea-Tiong,Sheu Shyh-Shyuan,Li Sih-Han,Lee Heng-Yuan,Chang Shih-Chieh,Yu Shimeng,Chang Meng-Fan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9046640/9062887/09062949.pdf?arnumber=9062949

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