A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA

Author:

Mousavi Mahsa,Pourshaghaghi Hamid Reza,Tahghighi Mohammad,Jordans Roel,Corporaal Henk

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays;Sensors;2024-08-19

2. Fault injection test on mitigated benchmark circuits using FPGA;AIP Conference Proceedings;2024

3. MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity;Microprocessors and Microsystems;2023-09

4. Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications;2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2021-10-06

5. PTA based availability analysis of the effects of blind scrubbing of UAV-UAV communication using SRAM based FPGAs;2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS);2021-09

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