Spatial Degradation Profiling Technique in Self-Aligned Top-Gate a-InGaZnO TFTs Under Current-Flowing Stress-Reference-Cited by-同舟云学术

Spatial Degradation Profiling Technique in Self-Aligned Top-Gate a-InGaZnO TFTs Under Current-Flowing Stress

Published:2023-01 Issue:1 Volume:44 Page:96-99
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Park Jingyu¹,Choi Sungju¹^ORCID,Myoung Seung Joo¹,Kim Jae-Young¹,Kim Changwook¹^ORCID,Choi Sung-Jin¹^ORCID,Kim Dong Myong¹^ORCID,Bae Jong-Ho¹^ORCID,Kim Dae Hwan¹^ORCID

Affiliation:

1. School of Electrical Engineering, Kookmin University, Seoul, South Korea

Funder

National Research Foundation of Korea (NRF) funded by the Ministry of Science, Information and Communication Technology (MSIT) of Korea Government

Technology Computer-Aided Design (TCAD) simulation SILVACO, Inc. and Integrated Circuit Design Education Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10001839/09967984.pdf?arnumber=9967984

Reference22 articles.

1. Bias-Dependent Effective Channel Length for Extraction of Subgap DOS by Capacitance–Voltage Characteristics in Amorphous Semiconductor TFTs

2. A Study on the Degradation of In-Ga–Zn-O Thin-Film Transistors Under Current Stress by Local Variations in Density of States and Trapped Charge Distribution

3. Hot-Carrier Effect on Amorphous In-Ga-Zn-O Thin-Film Transistors With a Via-Contact Structure

4. Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

5. Method to Extract Interface and Bulk Trap Separately Over the Full Sub-Gap Range in Amorphous InGaZnO Thin-Film Transistors by Using Various Channel Thicknesses

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