Author:
Blaquiere Y.,Dagenais M.,Savaria Y.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
2 articles.
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1. Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis;Lecture Notes in Computer Science;2006
2. VSPEC constraints modeling and evaluation;Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems