Exploring instruction caching strategies for tightly-coupled shared-memory clusters-Reference-Cited by-同舟云学术

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Exploring instruction caching strategies for tightly-coupled shared-memory clusters

Published:2011-10 Issue: Volume: Page:
ISSN:
Container-title:2011 International Symposium on System on Chip (SoC)
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Author:

Bortolotti Daniele,Paterna Francesco,Pinto Christian,Marongiu Andrea,Ruggiero Martino,Benini Luca

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6085645/6089208/06089691.pdf?arnumber=6089691

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2. The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores;IEEE Transactions on Multi-Scale Computing Systems;2018-04-01

3. Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures;Journal of Systems Architecture;2017-01

4. Exploring Embedded Symmetric Multiprocessing with Various On-Chip Architectures;2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing;2015-10

5. Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters;Proceedings of the 12th ACM International Conference on Computing Frontiers;2015-05-06

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