Analysis of 32-Bit Multiply and Accumulate unit (MAC) using Vedic Multiplier
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9070069/9077582/09077837.pdf?arnumber=9077837
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing;Journal of Circuits, Systems and Computers;2024-04-10
2. Evaluation of Novel 16-Bit Vedic Multiplier Using Carry Look Ahead Adder for High Speed and Low Area in Comparison with Carry Select Adder;2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2024-01-24
3. Implementation of a 32-bit MAC unit in AISC flow using Vedic Multiplier and CSA;2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2024-01-24
4. Analysis of Multiply-Accumulate (MAC) Unit Using Convolution Neural Networks (CNN);Lecture Notes in Networks and Systems;2024
5. Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24
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