Author:
Enjapuri Sriharsha,Gujjar Deepesh,Sinha Sandipan,Halli Ramesh,Trivedi Manish
Cited by
6 articles.
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1. A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
2. An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
3. A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications;Active and Passive Electronic Components;2023-11-07
4. Design and Characterization of 6T SRAM bitcell using 18nm FinFET;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13
5. SRAM Compilation and Placement Co-Optimization for Memory Subsystems;Electronics;2023-03-12