An Optimal Design for 1.2kV 4H-SiC JBSFET (Junction Barrier Schottky Diode Integrated MOSFET) With Deep P-Well-Reference-Cited by-同舟云学术

An Optimal Design for 1.2kV 4H-SiC JBSFET (Junction Barrier Schottky Diode Integrated MOSFET) With Deep P-Well

Author:

Kim Dongyoung¹^ORCID,Jang Seung Yup¹^ORCID,DeBoer Skylar¹,Morgan Adam J.¹^ORCID,Sung Woongje¹^ORCID

Affiliation:

1. College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY, USA

Funder

Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, the Vehicle Technologies Program Office

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

Reference18 articles.

1. P-type and N-type channeling ion implantation of SiC and implications for device design and fabrication;das;Electrochem Soc Trans,2020

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4. High-temperature Electrical Characteristics of JBS-integrated 4H-SiC MOSFETs;2023 IEEE 18th Conference on Industrial Electronics and Applications (ICIEA);2023-08-18