New Strained Lateral MOSFET With Ultralow On-Resistance by Surrounded Stress Dielectric Layer-Reference-Cited by-同舟云学术

New Strained Lateral MOSFET With Ultralow On-Resistance by Surrounded Stress Dielectric Layer

Published:2022-04 Issue:4 Volume:43 Page:525-528
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Li Mingzhe¹^ORCID,Duan Baoxing¹^ORCID,Yang Yintang¹^ORCID

Affiliation:

1. Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an, China

Funder

Science Foundation for Distinguished Young Scholars of Shaanxi Province

Higher Education Discipline Innovation Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/9741089/09726243.pdf?arnumber=9726243

Reference26 articles.

1. A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing

2. On the relation between deposition conditions and (mechanical) stress in plasma silicon nitride layers

3. Stress in silicon at Si3N4/SiO2film edges and viscoelastic behavior of SiO2films

4. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

5. Electrical and physico-chemical characterization of HfO2/SiO2 gate oxide stacks prepared by atomic layer deposition

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