Author:
Li Jin-Fu,Tsai Tsai-Ling,Hsu Chun-Lung,Sun Chi-Tien
Funder
Ministry of Science and Technology
Cited by
7 articles.
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1. Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
2. Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture;2023 IEEE European Test Symposium (ETS);2023-05-22
3. Structured Test Development Approach for Computation-in-Memory Architectures;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08
4. Testing and Reliability of Computing-In Memories: Solutions and Challenges;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08
5. Fault Modeling and Testing of RRAM-based Computing-In Memories;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08