Testing and Reliability of Computing-In Memories: Solutions and Challenges
Author:
Affiliation:
1. National Central University,Advanced Reliable System (ARES) Lab.,Department of Electrical Engineering,Taoyuan,Taiwan,320
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9946294/9946242/09946314.pdf?arnumber=9946314
Reference34 articles.
1. Resistive memory variability: A simplified trap-assisted tunneling model
2. Understanding error propagation in deep learning neural network (DNN) accelerators and applications
3. Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors
4. Rebooting Computing: The Challenges for Test and Reliability
5. Defect and Fault Modeling Framework for STT-MRAM Testing
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4. Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
5. Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
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