Design and Optimization of High Performance SRAM Based on 110nm Process

Author:

Ma Lijun.1,Zhang Lijun.1,Lou Yuan.1,Xie Dongdong.1,Zhang Zhongda.1,Chai Yongjian.1,Yan Yuling.1

Affiliation:

1. School of Rail Transportation, Soochow University,Suzhou,P. R. China

Publisher

IEEE

Reference10 articles.

1. A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters;yihan;Japanese Journal of Applied Physics,2022

2. High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing;pi-ho hu;2021 IEEE International Electron Devices Meeting (IEDM),2021

3. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

4. A 23.6-Mb/mm2 SRAM in 10 nm FinFET technologywith pulsed-PMOS TVC and stepped-wl for low-voltageapplications;guo;IEEE Journal of Solid-State Circuits,2018

5. Analysis of Low Power Reduction Techniques on Cache(SRAM) Memory

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