Performance Analysis of FinFET-Based Static Random Access Memory Design
Author:
Affiliation:
1. G H Raisoni College of Engineering and Management,Department of E&TC Engineering,Pune,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10083316/10083513/10083774.pdf?arnumber=10083774
Reference12 articles.
1. A low-power single-ended SRAM in FinFET technology
2. Physics-based device-circuit cooptimization scheme for 7-nm technology node SRAM design and beyond;qiang;IEEE Transactions on Electron Devices,2020
3. A novel four-transistor SRAM cell with low dynamic power consumption;arash;International Journal of Electronics Circuits and Systems (IJECS),2008
4. Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage
5. A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length
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