Author:
Arakali Abhijith,Talebbeydokthi Nema,Gondi Srikanth,Hanumolu Pavan Kumar
Cited by
3 articles.
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1. A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01
2. A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator;IEEE Transactions on Circuits and Systems II: Express Briefs;2012-12
3. Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-11