Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation-Reference-Cited by-同舟云学术

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Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation

Published:2015-03 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
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Author:

Hoy Chen-Han,Govindarajuz Venkatraman,Nowatzki Tony,Nagaraju Ranjini,Marzec Zachary,Agarwal Preeti,Frericks Chris,Cofell Ryan,Sankaralingam Karthikeyan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7093633/7095632/07095806.pdf?arnumber=7095806

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Improved Condition Handling in CGRAs with Complex Loop Support;Architecture of Computing Systems;2023

2. OverGen: Improving FPGA Usability through Domain-specific Overlay Generation;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

3. Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation;IEEE Transactions on Parallel and Distributed Systems;2022-06-01

4. NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17

5. Increasing Reliability Using Adaptive Cross-Layer Techniques in DRPs: Just-Safe-Enough Responses to Reliability Threats;Dependable Embedded Systems;2020-12-10

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