Cryo-CMOS Compact Modeling
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9371868/9371888/09371894.pdf?arnumber=9371894
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. DC-biased Suzuki stack circuit for Josephson-CMOS memory applications;Superconductor Science and Technology;2024-07-18
2. Methodologies for Device Characterization in Cryogenic Temperatures;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09
3. A New Framework to MOS Device for Cryogenic Application: Linking Materials with Modeling;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
4. Gaussian process-based device model toward a unified current model across room to cryogenic temperatures;2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS);2024-04-15
5. An Experimentally Verified Temperature Dependent Drain Current Fluctuation Model for Low Temperature Applications;IEEE Journal of the Electron Devices Society;2024
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