Lock-in Thermography judgment for short/leakage/high resistance defects in advanced Fan-Out packages
Author:
Affiliation:
1. Advanced Semiconductor Engineering, Inc. 26,Kaohsiung, Taiwan,R.O.C,811
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10457288/10457581/10457660.pdf?arnumber=10457660
Reference6 articles.
1. SLIM (TM), High Density Wafer Level Fan-Out Package Development with Submicron RDL
2. First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration
3. Power Plane Defect Findings in Silicon with Lock- In Thermography & OBIRCH/TIVA Techniques
4. The Application of Thermal Sensor to Locate IC Defects in Failure Analysis
5. Defect Location and Physical Analysis in Chip-on-chip Device
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